Signal integrity of a PCB training

Signal integrity problems may arise at many levels: within an IC, at the package level, on a PCB, at the backplane of boards, at inter-system communication.

There are issues that hold at various of these levels. This course concentrates on signal integrity on the PCB and around the interface between IC and PCB and is therefore highly relevant both for a board designer and an IC designer. The examples applied during the course, however, stem from the PCB area. The course does not cover aspects as architectures for fast systems.

There are problems on signal integrity (and power integrity) that manifest themselves on a PCB but that should have been resolved on an IC. In case an IC strongly radiates (EMC), there are additional costs at PCB-level such as with housing or a metal shield, possibly the required performance may even not be reached. To prevent these problems the board designer might choose a chip set from another supplier.

Furthermore, a relationship exists between the pinning of an IC and the number of layers of a PCB. For financial reasons there is a strong preference for e.g. a 4 layers board compared with a 6 layers count board (costs are rising sharply with the number of layers). However, this can make demands on the pinning. If these demands are not handled properly, a 6 layer PCB might be necessary because of SI reasons. An alternative is to select an IC from another supplier.

Lessons:

• Signal integrity: high speed signal propagation, reflection, ringing, transmission-lines, termination, balanced lines, edge control, crosstalk, stack-up, simulation of high speed nets;
• Power integrity: high speed power distribution, power planes topology, board stack-up planning, PCB production and materials, bypassing capacitors, embedded passives, power supply noise classes, power integrity simulation demo;
• IBIS modelling: creating IBIS models, modifying models, understanding the most important parameters of an IBIS model;
• EMC introduction: EMC compliance tests, emission, immunity to RF fields, EFT, bursts, pre-compliance testing, ESD, latch-up;
• EMC signals: identify the sources of radiation, narrow spectra signals versus wide spectra signals, clamping noise, board stack-up improvements for EMC, crosstalk;
• EMC coupling and cabling: ground bounce, VCC coupling, optimization of cable connections to a board, antenna's, radiation gain caused by cavities;
• EMC advanced partitioning: noise sources, SNR, common mode radiation versus differential mode, common mode isolation, unshielded housing, aperture antennas, creating common mode quite islands (moats).
• Signal Integrity and Timing analysis for DDRx. Layout guideline for first time right DDRx implementation.

Hands-on sessions:

• Transmission line termination simulations, simulation of different board layer stack-ups;
• IBIS modelling, IBIS modelling theory, debugging IBIS models + IBIS editor;
• Topology simulation, board partitioning, crosstalk analysis.
• Power Integrity Simulation- DC Drop, AC Decoupling analysis and optimization to suppress inductive peaks.