Advanced Thermal Management of Electronics

New technical developments bring greater thermal challenges, requiring advanced thermal management. Data centers, cloud and AI push component heat dissipation to new levels. The energy sector and variable drives in machinery and transportation also generate high heat losses. Without proper cooling, rising temperatures reduce performance, reliability, and lifespan. While fan-cooled heatsinks may be sufficient in some cases, liquid cooling is often necessary.

This training stands out due to:

  • its focus on advanced topics – liquid cooling, two-phase systems, digital design optimization.
  • hands-on guided exercises (steady-state, transient, forced-air and liquid cooling) which ensure direct application of theory.
  • international peer group fostering global knowledge exchange and cross-industry insights.
  • worked exercises that provide how-to examples of common engineering calculations for future reference.
  • trainer and renowned expert Wendy Luiten, with extensive domain knowledge through decades of industry experience.

This advanced training is available for open enrollment as well as for in-company sessions. For in-company sessions, the training can be adapted upon request, for instance by adding a tailor-made case study or an extra practice day.

Applied Statistics for R&D

Applied statistics is a key enabling skill in Research and Development. From setting up the experiments with adequate statistical power in early research, to design exploration, optimization and tolerance analysis in development and engineering – all phases in R&D benefit from correct application of appropriate statistical tools.

This training stands out due to:

  • Practical R&D toolkit: combining GRR measurement error, confidence intervals, sample size estimation, DOE,  multi-response optimization, Monte Carlo tolerancing— tailored to research and product development contexts.
  • Hands-on Minitab/Excel exercises: ensures immediate skill application.
  • Hands on fun Gage R&R exercise, Hands on fun DOE/ Optimization exercise
  • Worked exercises which provides how-to examples of common engineering calculations for future reference.
  • trainer and renowned expert Wendy Luiten, with extensive domain knowledge  through decades of industry experience.

In research and early development, measurement statistics are used to obtain the measurement error and subsequently calculate a sample size that large enough to obtain sufficient statistical power– the ability to see an effect if it is present. For example, using duplicate measurements, the power of finding a difference between two prototypes when the difference is about equal to the measurement error is below 10%. Underpowered experiments are undesirable because they result in a waste of time and money. Pursuing an underpowered experimental has no merit as it will not yield a repeatable result, instead either the measurement needs to be improved to reduce the error, or the sample size needs to increase, i.e., experiments have to be repeated more often.

In later development and in engineering, activities pursue fulfilling a function in terms of a specific output parameter ending up inside a required range. Failure rate is the proportion of instances where the output is outside of the desired specification window and the intended function is not fulfilled as required. A high failure rate is undesirable, it is a hallmark of bad quality and carries a financial penalty.

Part of the failure rate is ‘designed in’ – it is the result of a combination of design choices and design input variations, resulting in a distribution of the output parameter that partly falls outside the specification limits. Direct measurement of this failure rate to guide design decisions is typically not feasible as it needs too many tests – for example, a failure rate of 1% implies that on average 100 tests need to be performed to see 1 failure. To see the designed-in failure rate with accuracy, many more tests are needed, and this is generally infeasible. This poses a dilemma: By the time you have sufficient data on the failure rate, the time window for changes in the design has already closed.

The timing dilemma is not uncommon, and not limited to statistical parameters. The general solution is to use a stand-in and resort to modelling, using calculated values instead of measured data – CAD modelling, Circuit modelling, FEM modelling and CFD modelling are all examples where a model is used to assess a design before direct testing is possible.  In the same way, statistical modelling is used to investigate statistical behaviour of a design when testing is not feasible. Statistical modelling is foundational to design optimization and robust design. Specific experimental designs are used to derive surrogate functions that model the expected output values as a function of design inputs. Next, the surrogate functions are used to optimize. Finally, the expected distribution of the output parameter and the resulting designed -in failure rate are obtained from the surrogate function and the distribution of the input parameters.

This training is designed to familiarize participants with relevant statistical tools and way of working using linked statistical tools in their daily jobs. The trainer is a certified Master Black Belt in Design for Six Sigma with 35+ years of industry experience in R&D. All statistics are demonstrated using Minitab (industry standard) and Excel. The training contains exercises on individual statistical tools and a group exercise practicing the way of working, using the tools in conjunction. The training focus is on correct application of appropriate statistical tools to achieve development goals: “You do not need to know the workings of the engine in order to drive a car from A to B”. The training applies to continuous numerical parameters and covers both physical experiments and virtual experiments like CFD or FEM simulations.

This training is available for open enrollments in Eindhoven as well as for in-company sessions all over the world. For in-company sessions, the training can be adapted to your situation and special needs.

Analog / Mixed-Signal Test and Design-for-Test for Integrated Circuits

Integrated circuits (ICs) are manufactured by a long sequence of high-precision and hence defect-prone processing steps. Each IC must undergo stringent electrical tests to weed out defective parts and guarantee outgoing product quality to the customer. The field of ‘Design-for-Test’ (DfT) focuses in the broad sense on developing economically adequate tests for ICs. The tests must ensure sufficient quality at acceptable test application costs, corresponding to the target application area (e.g., wireless consumer products have less stringent quality requirements, but also different test cost budgets than medical or aerospace products).

Analog and mixed-signal (A/MS) ICs require different testers than for digital ICs, as well as different DfT techniques, measures of test quality, fault simulation, and test programs. Until quite recently, there has been very little automation to address these differences, mostly due to a lack of standardization in defining analog faults and defects, measuring a test’s coverage, test access to ICs, and DfT circuitry. This course teaches the principles of practical A/MS DfT and test, and the imminent IEEE standards that facilitate systematic solutions now and eventually much more automation.

This course is presented by a world-renowned speaker in the field with broad scientific and industrial experience: Stephen Sunter, Engineering Director for Mixed Signal DfT at Siemens EDA.

His course stands out due to the fact that:

· it is highly practical: combining specification-based and structural tests for manufacturing defects and functional safety;

· it has an industry-standard focus: up-to-date details on IEEE 2427 (defect coverage) and P1687.2 (analog IJTAG);

· it is taught by someone who has worked in A/MS design, testing, and DfT, for almost 50 years, and has been Chair or Vice-Chair of the three IEEE Working Groups for A/MS DfT standards.

This training is available for open enrollment as well as for in-company sessions. For in-company sessions, the training can be customized to fit your specific situation and requirements.

Power Integrity for Product Designers

Electronic systems are becoming faster, denser, and more power-hungry, making Power Distribution Network (PDN) design increasingly complex. With more supply voltages, tighter timing and noise margins, and rising interconnect density, power integrity can no longer be treated separately from signal integrity and EMC. A well-designed PDN is now essential for maintaining signal quality and electromagnetic compatibility. This course addresses board-level power distribution from a power integrity perspective, using minimal math and practical examples.

This course stands out due to:

  • Product-design focus: The clear emphasis on the entire PDN path—from IC to PCB layout—directly supports product designers;
  • IC <> PCB Interface insight: This bridging of roles between IC and board designers helps teams align across design domains, which is often overlooked but critical for real-world integration.
  • Real-time problem solving with PI analysis to mitigate EMI/EMC by managing return paths and decoupling strategies
  • Tool-neutral, practical approach: vendor-independent positioning makes the training accessible and adaptable to different company environments.
  • Experienced instructor blending process and hands-on techniques: The mix of theory, tools, and direct application ensures content is retained and implemented effectively.

This training is available for open enrollment as well as for in-company sessions. For in-company sessions, the training can be adapted to your situation and special needs.

Electronics Cooling Thermal Design

As industry pushes for more functionality, performance, miniaturization, and lower costs, heat densities rise—leading to higher temperatures that harm performance, reliability, and lifespan. This makes thermal design increasingly critical.

Optimizing thermal design is essential across applications like consumer electronics, semiconductors, power electronics, LEDs, automotive, data centers, and the Internet of Things.

This training stands out due to:

  • Model‑based system-level thermal design, with emphasis on integration of electronics and mechanical design.
  • Learning by doing: live, interactive practical exercises and two case studies of modelling and analyzing a thermal system design.
  • International peer group fostering global knowledge exchange and cross-industry insights.
  • Worked exercises provide how-to examples of common engineering calculations for future reference.
  • Taught by renowned expert Wendy Luiten, extensive domain knowledge through decades of industry experience.
     

Origin of the course
The famous 20+year old 3-day classroom course, originally intended for inexperienced as well as experienced participants, has been replaced by two modules to meet the requirements of modern times.

We kept the excellent and high-quality contents. We addressed feedback from our previous trainings to change the original course:

  • split up the thermal design part and the advanced cooling topics part;
  • add much more time to digest the theory;
  • provide more opportunities for hands-on practice;
  • spend more time on current and future electronic cooling solutions.

The thermal design module allows for sufficient opportunities for practicing and achieving an active skill level for designing new thermal applications, evaluating existing thermal applications, and assessing computational simulation models.

The advanced part builds on this foundation and is scheduled several weeks later. This provides more time to get familiar with the material and facilitates the uptake of the advanced material.

We strongly advice not to attend only the thermal design part since the advanced thermal management course gives very valuable additional information to assist in preventing thermal problems.

Both trainings are available for open enrollment as well as for in-company sessions. For in-company sessions, the training can be adapted to your situation and special needs.

Test and Design-for-Test for Digital Integrated Circuits

Integrated circuits (ICs) are integral part of any electronics system we see around. While the continue scaling of transistor feature sizes has been enhancing the chip density, the complexity of new generations of VLSI chips have been increasing; we already reached the point where billions of transistors are integrated on a single chip. Developing, designing and manufacturing of such chips are not only very complicated and time consuming, but also prone to defects; these may due to several deficiencies in the original silicon and in the manufacturing process. To guarantee the customers satisfaction, semiconductor companies have to ensure the required product quality and reliability of the manufactured chips through testing (e.g., at wafer level and after packaging). Moreover, It has been shown that tackling problems associated with testing VLSI chips at earlier design stage levels significantly reduces the testing cost. Thus it is important for hardware designers to be exposed to concepts of VLSI testing which can help them design better products at lower cost. Hence, appropriate test development is of key importance not only to ensure the customer satisfaction, but also to optimize the test cost.

This course covers the fundamentals of IC test and Design-for-Test; it introduces the participant to the field of digital systems testing and associated aspects. The participant will learn that ensuring customer satisfaction needs appropriate countermeasures to be taken, both during the design phase (i.e., part of the design), but also after manufacturing, and even in field/ during the lifetime of the application (i.e., continue  monitoring and acting when needed).  The course will teach the participant how to guarantee that a chip that may consists of billions of transistors and connections can be tested in e.g., less than one second,  how to ensure that the lifetime of the chip is 10 years rather than 2 years, etc.  Topics that will covered include: importance of VLSI test, test process and Automatic Test Equipment (ATE), defects and fault modelling, Fault simulation, Testability Measurements, Combinational Circuit Testing, sequential Circuit Testing, Memory Testing, Design for Testability, Scan Design, Boundary Scan, Built-in-Self Test, Delay Test, Current Testing, IC reliability, etc.

The presenter of this course is a world-renowned speaker in the field with broad scientific and industrial experience. The speaker has presented his course material at many international conferences, as well at leading semiconductor companies (in Asia, USA, and Europe).

This training is available for open enrollment as well as for in-company sessions. For in-company sessions, the training can be adapted to your situation and special needs.

Signal Integrity of a PCB workshop

Electronic devices become faster and smaller causing a strong increase of interference. The \”fast edges\” of modern electronic devices cause a lot of signal integrity (SI) problems. It is more and more difficult to use components within their specifications. The SI problems result in unexpected behavior of the hardware, reset problems, latch-ups, software hang-ups caused by the hardware and, last but not least, very noisy boards not compliant to FCC (USA), CISPR (EU) or VCCI (Japan).

This course stands out due to:

•highly applied, practical approach: Uses real hands-on modelling and simulation (HyperLynx);
•comprehensive coverage: Includes DDRx analysis, SerDes, timing, PI/EMC interactions;
•balanced SI with EMC/PI context: Teaches how SI fixes influence EMC and PI—interpreting cross-domain effects;
•very valuable for electronic designers, board layout experts, IC designers – bridging hardware/software perspectives;
•two experienced trainers who bring up-to-date knowledge and valuable insights to the course.

In this very practical course, the theory behind signal integrity is explained and illustrated, practical problems are modelled, simulated and analyzed, solutions are discussed, a way of working is proposed to minimize SI-problems. Electronic designers and board layout designers need to be aware of each other problems and approaches to solve and prevent SI-problems.

Demonstrations of analysis of problems are given with Hyperlynx. During the hands-on sessions, the course participants use Hyperlynx software to analyze system parts with SI problems and the effect of measures to reduce the SI-problems. Hyperlynx is a high-quality tool (in combination with technology files) for EMC, SI and PI-simulation. Note: the course is not a tool-training course.

Measures to improve SI cannot be done in isolation without paying attention to EMC and Power Integrity (PI). These SI measures can have a negative impact on EMC and PI. SI is the main topic of this course but potential negative consequences for EMC and PI are also discussed.

Note: The design of a power distribution network on a board is the main topic of the PI-course.

This training is available for open enrollment as well as for in-company sessions. For in-company sessions, the training can be adapted to your situation and special needs.

Ultra Low Power hands-on workshop

Energy consumption has become a primary design constraint, along with performance and clock frequency:

  • A multitude of devices are connected through the Internet (Internet of Things – loT);
  • Many devices communicate wirelessly and run on batteries;
  • European laws become stricter about energy.

We need to use much less energy.
This workshop shows that the energy consumption can be reduced drastically provided we work on a systematic and holistic way.

Energy consumption is a system issue with many consumption influencing factors. A gain on one place can create a loss on another place. It is a matter of balancing and making compromises.

Significant lower energy consumption can only be achieved by proper design at all levels of abstraction: from architectural design to component selection and physical implementation, but also through careful use and control of the operating system and careful design of application programs. Power management and functionality are interwoven and ask for a real time control.

This hands-on workshop gives a broad and systematic overview of the overwhelming possibilities for ultra low power design. More experienced people can also benefit from this course because of the overview and the many hints and tips.

Various hardware blocks are discussed from the perspective of their possibility to consume less power: MCU’s, memory/processor/I-O, sensors & interfacing, radio, energy sources, regulators. Energy reduction possibilities are discussed on various levels:

  • Guidelines for MCU selection;
  • System architecture: balance between the location of data processing and data transport, distribution of activities in the pipeline of a system;
  • Balance between performance and energy consumption;
  • Effects of compiler and linker settings;
  • Software mapping onto memory modules dependent on their speed and consumption and on time critical routines (e.g. analysis of the effect of alignment);
  • Instruments (hardware tooling, benchmarks) are used to measure the energy consumption before and after the introduced changes.

The lecturer (advanced expert at Capgemini Engineering) has a broad and in-depth hardware-software engineering experience (in research and development, feasibility studies, system performance tuning), has acted a lot on the border between hardware and software and is an advisor of the EEMBC Working Groups ULPMark, IoTMark-BLE and SecureMark-TLS. (EEMBC defines Industry-Standard Benchmarks for Embedded Systems). Other activities the trainer is involved in: participated in the ULP group at Holst Center for 2 years, (co-)author of several papers in the area of parallel programming using the Communicating Sequential Processes paradigm and the use of Analytical Software Design / Dezyne, regularly gives guest lectures at universities, polytechnics and at various conferences, defines graduation projects and coaches students.

The ‘Ultra Low Power’ hands-on workshop:

  • Identifies factors that influence energy consumption;
  • Shows how to model and measure energy consumption;
  • Provides an overview of available energy measurement tooling;
  • Provides an overview of how to reduce the energy footprint;
  • Gives a guideline for MCU selection;
  • Gives a design process use case on how to investigate and apply the energy reduction techniques in a systematic way;
  • Provides hands-on sessions to anchor the obtained knowledge.

 

EMC Design Techniques

Electromagnetic compatibility (EMC) is essential in today’s increasingly complex electronic systems. A failure to meet EMC requirements—whether regulatory or customer-specific—can delay product launches and lead to costly redesigns. This training helps engineers avoid those pitfalls by equipping them with practical EMC knowledge, tools, and techniques.

This training stands out due to:

  • Immediate practical value: hands-on workshop on day 4 turns theory into real-world skills
  • Live demonstrations: numerous in-class demos bring abstract EMC concepts to life
  • Compact & effective: high-impact 4-day format – ideal balance of dept and efficiency
  • Experienced instructors: industry professionals with deep practical EMC expertise
  • Early design integration: emphasis on designing EMC from the start to avoid late-stage surprises (DC – 6 GHz)

This intensive four-day course provides a strong theoretical foundation along with hands-on experience in identifying, analyzing, and solving EMC problems. You’ll explore a wide frequency range—from DC up to 6 GHz—and examine real-world solutions using actual product scenarios. The program concludes with a full-day workshop where participants apply what they’ve learned to practical EMC cases in small teams. 

Whether you’re working in product development, system engineering, or quality assurance, this course provides you with critical insights to improve product reliability, reduce emissions, and ensure immunity from electromagnetic disturbances.

This training is available for open enrollment as well as for in-company sessions. For in-company sessions, the training can be adapted to your product context and specific needs.

IC Physics, Devices and Processing

A basic knowledge of semiconductor physics and devices and of IC processing is needed for quite a number of functions: from IC technology engineers to test and product engineers and IC designers. 

This course is an introduction course and lays the foundation and focuses on the relation between the semiconductor technology and the behavior of the devices.

This training is available for open enrollment as well as for in-company sessions. For in-company sessions, the training can be adapted to your situation and special needs.